1. Technical Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a pad structure, pad layout structure and layout method in a semiconductor device.
2. Description of the Related Art
In semiconductor devices, particularly semiconductor memory devices, pads are provided to electrically connect a semiconductor memory device to external devices. Through the pads, signals including command signals, data read signals, and data write signals are input to or output by the device.
There is a continuing trend toward high integration in semiconductor memory devices and a corresponding reduction in design rule. Such high integration reduces the size of a semiconductor memory device, increasing the number of net dies produced from a semiconductor wafer and thereby reducing cost.
However, even though the degree of integration of devices increases, for example twofold, the number of pads generally does not increase at the same rate as the number of devices. Also, where the degree of integration is reduced by half, the number of pads is not reduced at the same rate as the number of devices. Thus, in a highly integrated device, the area occupied by the pads is generally not a significant issue, but in a relatively low-integrated device as compared with the high integrated device, the area occupied by the pads becomes an important issue. Accordingly, the semiconductor device manufacturing process has increasingly advanced with a continuous reduction in chip size, without a decrease in the size of pads. In other words, even though the overall size of the chip is reduced, the size of the pads cannot be readily decreased, since there is a strong investment required for updating bonding equipment and test equipment that are configured for a certain size pad.
FIG. 1 schematically illustrates a semiconductor memory device having pads according to a conventional configuration.
Referring to FIG. 1, a semiconductor memory device 10 includes a memory cell array MCA, and pad groups formed on a peripheral region of the memory cell array MCA. The memory cell array MCA includes unit memory cells formed on intersections of bit lines and word lines and disposed in a matrix type.
The pad group PG3 includes pads PD1, PD2, PD3, . . . , PDn-2, PDn-1 and PDn. The pad group PG4 includes pads PD11, PD12, PD13, PD14, . . . , PDm-2, PDm-1 and PDm. The pads PD1, PD2, PD3, . . . , PDn-2, PDn-1, PDn, PD11, PD12, PD13, PD14, . . . , PDm-2, PDm-1 and PDm provide an electrical connection between the semiconductor memory device 10 and external devices.
More in detail, the pads PD1, PD2, PD3, PDn-2, PDn-1, PDn, PD11, PD12, PD13, PD14, PDm-2, PDm-1 and PDm can be divided into: pads for testing the semiconductor memory device 10; pads for wire bonding the device with external devices; pads that are used for testing of the semiconductor memory device 10 but are not used for wire bonding, and pads that are used only for wire bonding. The test is executed using test equipment performing procedures that, following contact of a probe tip with the pad, cause signals related to a command input and data read and data write operations etc. to be input to the semiconductor memory device 10, or to be output by the device 10. The wire bonding pads are connected with a lead frame of a package, e.g., plastic package, through a metal line, e.g., gold wire, in a package bonding process.
In a peripheral region adjacent to the pad region, peripheral circuit devices for operation of the semiconductor memory device, e.g., buffers, a delay devices, MOS (Metal Oxide Semiconductor) transistors etc., are formed.
FIG. 2 is a schematic view illustrating an enlargement of pads shown in FIG. 1.
With reference to FIG. 2, pads PD11, PD12, PD13 and PD14, and a pad pitch PAD_PIT, are shown. Reference characters T1, T2, T3 and T4 indicate probe marks as portions recessed by a contact of probe tip.
The pads can be generally classified into pads that are used for testing of the semiconductor memory device and are used for wire bonding the device with external devices, and pads that are used only for testing and are not used for wire bonding of the semiconductor memory device. For example, the pad PD11 may be a wire bonding pad, the pad PD12 may be a non-wire bonding pad, the pad PD13 may be a wire bonding pad, and the pad PD14 may be a non-wire bonding pad. Or, the pad PD11 may be a wire bonding pad, the pad PD12 may be a wire bonding pad, the pad PD13 may be a wire bonding pad, and the pad PD14 may be a non-wire bonding pad. Both the pads to be bonded and not to be bonded are formed to have the same, uniform size. In other words, in the pads PD11, PD12, . . . , wire bonding pads are not distinguished from non-wire bonding pads.
The pad pitch PAD_PIT indicates a distance between adjacent pads, and is related to a width margin for formation of a pad. For example, a pad pitch PAD_PIT between the pad PD11 and the pad PD12 is from the left end of the pad PD11 to the left end of the pad PD12. Generally, the sizes of the pads PD11, PD12, PD13, and the pad pitch, are substantially uniform throughout a device.
Wire bonding is generally performed by evading probe marks that are caused by a portion recessed by a probe tip. If the probe mark is contacted in the bonding process, adhesion between the pads and a bonding wire can become weak, causing a decrease in package yield.
In the pads shown in FIGS. 1 and 2, the bonding pads have also been used for testing procedures, where a probe has come in contact with the pad at locations T1, T2, T3, T4, thus the basic size of the bonding pads including probing regions 11, 13, 15 and 17 of FIG. 2, and wire bonding regions 12, 14, 16 and 18 of FIG. 2, should be guaranteed. For pads that are not bonded, only a smallest region for probing 11, 13, 15, 17 is ensured.
In such a conventional semiconductor memory device described above, the sizes of pads used for testing but not used for a wire bonding, and of pads used for both test and wire bonding, are substantially uniform, thus it is difficult to increase pad pitch within a determined region.
Further, since pads used for testing but not used for a wire bonding, and pads used for both testing and wire bonding, have a substantially uniform size, it is difficult to reduce the size of a pad region where the pads are formed, causing a limitation for a size reduction, and integration degree, of semiconductor memory devices. Such problems occur not only in semiconductor memory devices and but also in other types of semiconductor devices, e.g., microprocessor, CCD etc., in which pads are formed.
In the meantime, limitations exist not only in the layout of pads, but also in the structure of pads. For example, a mesh and non-mesh pad structure of conventional pads can lead to many problems. The problems will be described as follows, referring to FIGS. 3A to 4B.
FIGS. 3A and 3B are schematic views illustrating a structure of one of the pads shown in FIG. 1. FIG. 3A is a plan view and FIG. 3B is a sectional view taken along section line A1-A2 of FIG. 3A.
Referring to FIGS. 3A and 3B, a pad PD1 has a non-mesh structure, and has a structure in which an interlayer insulation layer 28 is formed on a semiconductor substrate 29, a first metal layer 26 is formed on the interlayer insulation layer 28, and a via layer 24 is formed on the first metal layer 26, piercing through an insulation layer between the first metal layer 26 and a second metal layer 22.
The second metal layer 22 is a portion of the pad that comes in contact with a probe tip, or is bonded to a wire, e.g., gold wire, in a packaging process.
In the pad PD1 of non-mesh structure, the via layer 24 connecting the first metal layer 26 to the second metal layer 22 is formed through the insulation layer. This type of structure is susceptible to open effects in a bonded portion in a wire bonding of the non-mesh structural pad PD1, for example, metal open, pad open, missing ball etc.
FIGS. 4A and 4B illustrate one type of pad to alleviate the shortcomings of the non-mesh structural pad shown in FIGS. 3A and 3B. FIG. 4A is a plan view of mesh structural pad, and FIG. 4B is a sectional view taken along section line B1-B2 shown in FIG. 4A.
With reference to FIGS. 4A and 4B, a pad PD30 of a mesh structure has a structure including an interlayer insulation layer 38 formed on a semiconductor substrate 39, and a first metal layer 36 is formed on the interlayer insulation layer 38. On the first metal layer 36, a plurality of contact plugs 34 are formed piercing an interlayer insulation layer 33, instead of forming a single via layer in the non-mesh structural pad example shown above in FIGS. 3A and 3B. The first metal layer 36 is then connected to a second metal layer 32 through the contact plugs 34.
The second metal layer 32 is a portion of the pad that comes in contact with a probe tip in a testing process or that is bonded to a wire in a packaging process, as in the non-mesh structural pad shown in FIGS. 3A and 3B. An upper surface of the second metal layer 32 is formed as an embossed surface referred to in FIG. 4A. Reference number 30 indicates a convex portion of the embossed surface.
As shown in FIGS. 4A and 4B, a mesh structure is applied to all portions of a determined pad region, and the structure of a pad is strengthened through use of the contact plugs 34, thereby reducing the likelihood of the occurrence of a metal open, a pad open and an open effect of missing ball, etc.
However, wear of the probe tip is common during test probing, due to the embossed surface of the mesh structure, and this causes an additional cost by necessitating the frequent change of probe cards.
Furthermore, particles are generated excessively in the contact of the probe tip with the pad, and a bonding force of the pad becomes weak in a wire bonding, which can result in the generation of defects in the operational characteristics of semiconductor memory devices and can lower package yield in the packaging process.
In addition, additional process time is required for probe tip cleaning in order to remove particles generated by probe tip contact, which can affect production costs of semiconductor memory devices.